1. Field of the Invention
The present invention relates to integrated circuits, and more particularly to a method and apparatus for connecting layers of integrated circuits.
2. Description of the Related Art
All computer chips today function as essentially two-dimensional arrays, with devices placed next to one another. Such an arrangement has significant disadvantages. For example, the number of devices on a chip grows as the inverse square of the size of the devices, but the number of connections of the chip can grow, at most, linearly with the inverse of the size. Thus, as the number of devices on a chip increases, there is more competition among the devices for communication lines on and off the chip, resulting in an increase in communication delays.
A solution to the problems presented by two-dimensional intergated circuits is to manufacture three-dimensional integrated circuits (3D ICs) with devices stacked in piles. Connections between one layer and the one underneath can grow as rapidly as the number of devices and be very short, significantly increasing overall speed compared with two chips sided by side. The layers of integrated circuits can be, for example, logic circuits, memory circuits, mixed-signal circuits, or sensors. In addition, devices can reside on different layers to form a complete circuit.